#ifndef _PARTHUS_HW_HAB_DEFS_
#define _PARTHUS_HW_HAB_DEFS_

/******************************************************************************
 * MODULE NAME:    hw_hab_defs.h
 * PROJECT CODE:   BlueStream
 * DESCRIPTION:    Register definitions for Habanero
 * MAINTAINER:     Ivan Griffin
 * CREATION DATE:  20 March 2000
 *
 * SOURCE CONTROL: $Id: hw_hab_defs.h,v 1.5 2008/11/08 07:30:01 tianwq Exp $
 *
 * LICENSE:
 *     This source code is copyright (c) 2000-2004 Ceva Inc.
 *     All rights reserved.
 *
 ******************************************************************************/

#include "sys_config.h"

#ifndef HAB_BASE_ADDR
#define HAB_BASE_ADDR JAL_BASE_ADDR
#endif

#define HAB_STOP_ADDR   (HAB_BASE_ADDR + 0x00010000)
#define HAB_WAIT_STATES 3
#define HAB_SEGMENT     5
#define HAB_ECE_HIGH    (1 << 9) /* CE4 High */
#define HAB_ECE_LOW     (1 << 8) /* CE4 Low  */



/***************************************************************************
 *
 * Define the bit positions for the Interface Configuration Registers 
 *
 ***************************************************************************/

#define HAB_PHY_CFG_ADDR             (0x0000004C + HAB_BASE_ADDR)
#define HAB_PHY_CFG_MASK             0xFFFFFFFF /* 32 bits */    
#define HAB_PHY_CFG_SHFT             0                           
                                                                 
#define HAB_REFCLK_DIV_ADDR          (0x0000004C + HAB_BASE_ADDR)
#define HAB_REFCLK_DIV_MASK          0x0000001F                  
#define HAB_REFCLK_DIV_SHFT          0                           
                                                                 
#define HAB_TAB_LPO_SEL_ADDR         (0x0000004C + HAB_BASE_ADDR)
#define HAB_TAB_LPO_SEL_MASK         0x00000020                  
#define HAB_TAB_LPO_SEL_SHFT         5                           
                                                                 
#define HAB_PHYCLK_GATE_ADDR         (0x0000004C + HAB_BASE_ADDR)
#define HAB_PHYCLK_GATE_MASK         0x00000040                  
#define HAB_PHYCLK_GATE_SHFT         6                           
                                                                 
#define HAB_LPOCLK_DIV_ADDR          (0x0000004C + HAB_BASE_ADDR)
#define HAB_LPOCLK_DIV_MASK          0x00000080                  
#define HAB_LPOCLK_DIV_SHFT          7                           
                                                                 
#define HAB_CRYSTAL_OFF_DELAY_ADDR   (0x0000004C + HAB_BASE_ADDR)
#define HAB_CRYSTAL_OFF_DELAY_MASK   0x00001F00                  
#define HAB_CRYSTAL_OFF_DELAY_SHFT   8                           
                                                                 
#define HAB_REFCLK_INV_ADDR          (0x0000004C + HAB_BASE_ADDR)
#define HAB_REFCLK_INV_MASK          0x00008000                  
#define HAB_REFCLK_INV_SHFT          15                          
                                                                 
#define HAB_CRYSTAL_ON_DELAY_ADDR    (0x0000004C + HAB_BASE_ADDR)
#define HAB_CRYSTAL_ON_DELAY_MASK    0x001F0000                  
#define HAB_CRYSTAL_ON_DELAY_SHFT    16                          
                                                                 
#define HAB_TX_INV_ADDR              (0x0000004C + HAB_BASE_ADDR)
#define HAB_TX_INV_MASK              0x00200000                  
#define HAB_TX_INV_SHFT              21                          
                                                                 
#define HAB_RX_INV_ADDR              (0x0000004C + HAB_BASE_ADDR)
#define HAB_RX_INV_MASK              0x00400000                  
#define HAB_RX_INV_SHFT              22                          
                                                                 
#define HAB_AUTO_WAKEUP_ADDR         (0x0000004C + HAB_BASE_ADDR)
#define HAB_AUTO_WAKEUP_MASK         0x07000000                  
#define HAB_AUTO_WAKEUP_SHFT         24                                                                                                   
                                                                         


/*
 * General IO Control General Purpose Register 1 Address 0x60
 */

#define HAB_GIO_HIGH_CTRL_1_AND_0_REG_ADDR        (HAB_BASE_ADDR + 0x140)
#define HAB_GIO_HIGH_CTRL_3_AND_2_REG_ADDR        (HAB_BASE_ADDR + 0x144)
#define HAB_GIO_HIGH_CTRL_5_AND_4_REG_ADDR        (HAB_BASE_ADDR + 0x148)
#define HAB_GIO_HIGH_CTRL_7_AND_6_REG_ADDR        (HAB_BASE_ADDR + 0x14c)
#define HAB_GIO_HIGH_CTRL_9_AND_8_REG_ADDR        (HAB_BASE_ADDR + 0x150)
#define HAB_GIO_HIGH_CTRL_B_AND_A_REG_ADDR        (HAB_BASE_ADDR + 0x154)

#define HAB_GIO_LOW_CTRL_1_AND_0_REG_ADDR         (HAB_BASE_ADDR + 0x158)
#define HAB_GIO_LOW_CTRL_3_AND_2_REG_ADDR         (HAB_BASE_ADDR + 0x15c)
#define HAB_GIO_LOW_CTRL_5_AND_4_REG_ADDR         (HAB_BASE_ADDR + 0x160)
#define HAB_GIO_LOW_CTRL_7_AND_6_REG_ADDR         (HAB_BASE_ADDR + 0x164)
#define HAB_GIO_LOW_CTRL_9_AND_8_REG_ADDR         (HAB_BASE_ADDR + 0x168)
#define HAB_GIO_LOW_CTRL_B_AND_A_REG_ADDR         (HAB_BASE_ADDR + 0x16c)

#define HAB_GIO_CTRL_COMB_3_2_1_0_REG_ADDR        (HAB_BASE_ADDR + 0x170)
#define HAB_GIO_CTRL_COMB_7_6_5_4_REG_ADDR        (HAB_BASE_ADDR + 0x174)
#define HAB_GIO_CTRL_COMB_B_A_9_8_REG_ADDR        (HAB_BASE_ADDR + 0x178)
/*
 * Reset Control General Purpose Register 1 Address 0x64
 */

#endif
